Design of Low-Power Coarse-Grained Reconfigurable Architectures

Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architect

Autorentext

Yoonjin Kim is an assistant professor in the Department of Computer Science at Sookmyung Women's University in Seoul, South Korea. Dr. Kim was previously a senior R&D staff member at Samsung Advanced Institute of Technology in Yongin, South Korea. He earned his Ph.D. in computer engineering from Texas A&M University. His research interests include embedded systems, computer architecture, VLSI/system-on-chip design, and hardware/software co-design.

Rabi N. Mahapatra is a professor in the Department of Computer Science and Engineering and director of the Embedded Systems and Codesign Laboratory at Texas A&M University in College Station. He is an associate editor of the ACM Transactions on Embedded Computing and an editorial board member of the International Journal on Information and Communication Technology. Dr. Mahapatra is also founder and chairman of the Bhubaneswar Institute of Technology (BIT) in India. His research interests include network on chip, system-on-chip reliability, low-power IP lookup architectures, and intention-based searching.

Inhalt

Introduction. Trends in CGRA. CGRA for High Performance and Flexibility. Base CGRA Implementation. Power Consumption in CGRA. Low-Power Reconfiguration Technique. Dynamic Context Compression for Low-Power CGRA. Dynamic Context Management for Low-Power CGRA. Cost-Effective Array Fabric. Hierarchical Reconfigurable Computing Arrays. Integrated Approach to Optimize CGRA. Bibliography. Index.