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A Pipelined Multi-Core Machine with Operating System Support

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This work is building on results from the book named 'A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correc... Weiterlesen
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Beschreibung

This work is building on results from the book named 'A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness' by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

• MIPS instruction set architecture (ISA) for application and for system programming

• cache coherent memory system

• store buffers in front of the data caches

• interrupts and exceptions

• memory management units (MMUs)

• pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

• I/O-interrupt controller and a disk

 



Klappentext

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

. MIPS instruction set architecture (ISA) for application and for system programming

. cache coherent memory system

. store buffers in front of the data caches

. interrupts and exceptions

. memory management units (MMUs)

. pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

. local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

. I/O-interrupt controller and a disk



Inhalt

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.

Produktinformationen

Titel: A Pipelined Multi-Core Machine with Operating System Support
Untertitel: Hardware Implementation and Correctness Proof
Autor:
EAN: 9783030432430
Digitaler Kopierschutz: Wasserzeichen
Format: E-Book (pdf)
Hersteller: Springer-Verlag GmbH
Genre: IT & Internet
Anzahl Seiten: 628
Veröffentlichung: 09.05.2020
Dateigrösse: 13.8 MB

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