High Performance Embedded Architectures and Compilers

As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

Inhalt

Invited Program.- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.- Software Defined Radio - A High Performance Embedded Challenge.- I Analysis and Evaluation Techniques.- A Practical Method for Quickly Evaluating Program Optimizations.- Efficient Sampling Startup for Sampled Processor Simulation.- Enhancing Network Processor Simulation Speed with Statistical Input Sampling.- II Novel Memory and Interconnect Architectures.- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.- Streaming Sparse Matrix Compression/Decompression.- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs.- III Security Architecture.- Memory-Centric Security Architecture.- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management.- Arc3D: A 3D Obfuscation Architecture.- IV Novel Compiler and Runtime Techniques.- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations.- Induction Variable Analysis with Delayed Abstractions.- Garbage Collection Hints.- V DomainSpecificArchitectures.- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors.- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture.- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.- A Low-Power DSP-Enhanced 32-Bit EISC Processor.