Inhalt
Plenary Keynotes.- FPGAs and the Era of Field Programmability.- Reconfigurable Systems Emerge.- System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?.- Organic and Biology Computing.- Hardware Accelerated Novel Protein Identification.- Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices.- Security and Cryptography 1.- A Key Management Architecture for Securing Off-Chip Data Transfers.- FPGA Implementation of Biometric Authentication System Based on Hand Geometry.- Platform Based Design.- SoftSONIC: A Customisable Modular Platform for Video Applications.- Deploying Hardware Platforms for SoC Validation: An Industrial Case Study.- Algorithms and Architectures.- Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes.- Power Analysis Attacks Against FPGA Implementations of the DES.- Acceleration Application 1.- Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer.- Stochastic Simulation for Biochemical Reactions on FPGA.- Architecture 1.- Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures.- Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine.- Improving FPGA Performance and Area Using an Adaptive Logic Module.- A Dual-V DD Low Power FPGA Architecture.- Physical Design 1.- Simultaneous Timing Driven Clustering and Placement for FPGAs.- Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.- Compact Buffered Routing Architecture.- On Optimal Irregular Switch Box Designs.- Arithmetic 1.- Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.- Comparative Study of SRT-Dividers in FPGA.- Second Order Function Approximation Using a Single Multiplication on FPGAs.- Efficient Modular Division Implementation.- Multitasking.- A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.- The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures.- Circuit Technology.- A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.- Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device.- Memory 1.- Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA.- Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays.- Network Processing.- A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks.- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs.- Testing.- BIST Based Interconnect Fault Location for FPGAs.- FPGAs BIST Evaluation.- Applications.- Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.- Evaluating Fault Emulation on FPGA.- Arithmetic 2.- Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.- Multiple Restricted Multiplication.- Signal Processing 1.- Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.- A Steerable Complex Wavelet Construction and Its Implementation on FPGA.- Computational Models and Compiler.- Programmable Logic Has More Computational Power than Fixed Logic.- JHDLBits: The Merging of Two Worlds.- A System Level Resource Estimation Tool for FPGAs.- The PowerPC Backend Molen Compiler.- Dynamic Reconfiguration 1.- An Integrated Online Scheduling and Placement Methodology.- On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.- Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases -.- Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.- Network and Optimization Algorithms.- Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems.- Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2.- Three-Dimensional Dynamic Programming for Homology Search.- An Instance-Specific Hardware Algorithm for Finding a Maximum Clique.- System-on-Chip 1.- IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.- Automatic Creation of Reconfigurable PALs/PLAs for SoC.- High Speed Design.- A Key Agile 17.4 Gbit/sec Camellia Implementation.- High Performance True Random Number Generator in Altera Stratix FPLDs.- Security and Cryptography 2.- A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.- Exploring Area/Delay Tradeoffs in an AES FPGA Implementation.- Architectures 2.- Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor.- Memory 2.- Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.- Storage Allocation for Diverse FPGA Memory Specifications.- Image Processing 1.- Real Time Optical Flow Processing System.- Methods and Tools for High-Resolution Imaging.- Network-on-Chip.- Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation.- A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data.- Power Aware Design 1.- A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems.- An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms.- IP-Based Design.- HW/SW Co-design by Automatic Embedding of Complex IP Cores.- Increasing Pipelined IP Core Utilization in Process Networks Using Exploration.- Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.- SOC and RTOS: Managing IPs and Tasks Communications.- Power Aware Design 2.- The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.- A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms.- Power-Driven Design Partitioning.- Power Consumption Reduction Through Dynamic Reconfiguration.- Coprocessing Architectures.- The XPP Architecture and Its Co-simulation Within the Simulink Environment.- An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer.- Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.- Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.- Embedded Tutorials.- Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.- SystemC for the Design and Modeling of Programmable Systems.- An Evolvable Hardware Tutorial.- Dynamic Reconfiguration 2.- A Runtime Environment for Reconfigurable Hardware Operating Systems.- A Dynamically Reconfigurable Asynchronous FPGA Architecture.- Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.- Physical Design 2.- Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.- Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs.- Automating the Layout of Reconfigurable Subsystems via Template Reduction.- Acceleration Application 2.- FPGA Acceleration of Rigid Molecule Interactions.- Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.- Exploring Potential Benefits of 3D FPGA Integration.- System Level Design.- System-Level Modeling of Dynamically Reconfigurable Co-processors.- A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.- Physical Interconnect.- Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.- Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs.- Computational Models.- Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware.- Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA.- Acceleration Applications 3.- Java Technology in an FPGA.- Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers.- The Chess Monster Hydra.- Arithmetic 3.- FPGA-Efficient Hybrid LUT/CORDIC Architecture.- A Multiplexer-Based Concept for …