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Field Programmable Logic and Application

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Inhalt Plenary Keynotes.- FPGAs and the Era of Field Programmability.- Reconfigurable Systems Emerge.- System-Level Design Tools C... Weiterlesen
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Inhalt

Plenary Keynotes.- FPGAs and the Era of Field Programmability.- Reconfigurable Systems Emerge.- System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?.- Organic and Biology Computing.- Hardware Accelerated Novel Protein Identification.- Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices.- Security and Cryptography 1.- A Key Management Architecture for Securing Off-Chip Data Transfers.- FPGA Implementation of Biometric Authentication System Based on Hand Geometry.- Platform Based Design.- SoftSONIC: A Customisable Modular Platform for Video Applications.- Deploying Hardware Platforms for SoC Validation: An Industrial Case Study.- Algorithms and Architectures.- Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes.- Power Analysis Attacks Against FPGA Implementations of the DES.- Acceleration Application 1.- Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer.- Stochastic Simulation for Biochemical Reactions on FPGA.- Architecture 1.- Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures.- Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine.- Improving FPGA Performance and Area Using an Adaptive Logic Module.- A Dual-V DD Low Power FPGA Architecture.- Physical Design 1.- Simultaneous Timing Driven Clustering and Placement for FPGAs.- Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.- Compact Buffered Routing Architecture.- On Optimal Irregular Switch Box Designs.- Arithmetic 1.- Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.- Comparative Study of SRT-Dividers in FPGA.- Second Order Function Approximation Using a Single Multiplication on FPGAs.- Efficient Modular Division Implementation.- Multitasking.- A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.- The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures.- Circuit Technology.- A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.- Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device.- Memory 1.- Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA.- Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays.- Network Processing.- A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks.- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs.- Testing.- BIST Based Interconnect Fault Location for FPGAs.- FPGAs BIST Evaluation.- Applications.- Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.- Evaluating Fault Emulation on FPGA.- Arithmetic 2.- Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.- Multiple Restricted Multiplication.- Signal Processing 1.- Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.- A Steerable Complex Wavelet Construction and Its Implementation on FPGA.- Computational Models and Compiler.- Programmable Logic Has More Computational Power than Fixed Logic.- JHDLBits: The Merging of Two Worlds.- A System Level Resource Estimation Tool for FPGAs.- The PowerPC Backend Molen Compiler.- Dynamic Reconfiguration 1.- An Integrated Online Scheduling and Placement Methodology.- On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.- Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases -.- Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.- Network and Optimization Algorithms.- Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems.- Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2.- Three-Dimensional Dynamic Programming for Homology Search.- An Instance-Specific Hardware Algorithm for Finding a Maximum Clique.- System-on-Chip 1.- IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.- Automatic Creation of Reconfigurable PALs/PLAs for SoC.- High Speed Design.- A Key Agile 17.4 Gbit/sec Camellia Implementation.- High Performance True Random Number Generator in Altera Stratix FPLDs.- Security and Cryptography 2.- A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.- Exploring Area/Delay Tradeoffs in an AES FPGA Implementation.- Architectures 2.- Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor.- Memory 2.- Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.- Storage Allocation for Diverse FPGA Memory Specifications.- Image Processing 1.- Real Time Optical Flow Processing System.- Methods and Tools for High-Resolution Imaging.- Network-on-Chip.- Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation.- A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data.- Power Aware Design 1.- A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems.- An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms.- IP-Based Design.- HW/SW Co-design by Automatic Embedding of Complex IP Cores.- Increasing Pipelined IP Core Utilization in Process Networks Using Exploration.- Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.- SOC and RTOS: Managing IPs and Tasks Communications.- Power Aware Design 2.- The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.- A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms.- Power-Driven Design Partitioning.- Power Consumption Reduction Through Dynamic Reconfiguration.- Coprocessing Architectures.- The XPP Architecture and Its Co-simulation Within the Simulink Environment.- An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer.- Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.- Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.- Embedded Tutorials.- Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.- SystemC for the Design and Modeling of Programmable Systems.- An Evolvable Hardware Tutorial.- Dynamic Reconfiguration 2.- A Runtime Environment for Reconfigurable Hardware Operating Systems.- A Dynamically Reconfigurable Asynchronous FPGA Architecture.- Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.- Physical Design 2.- Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.- Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs.- Automating the Layout of Reconfigurable Subsystems via Template Reduction.- Acceleration Application 2.- FPGA Acceleration of Rigid Molecule Interactions.- Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.- Exploring Potential Benefits of 3D FPGA Integration.- System Level Design.- System-Level Modeling of Dynamically Reconfigurable Co-processors.- A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.- Physical Interconnect.- Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.- Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs.- Computational Models.- Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware.- Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA.- Acceleration Applications 3.- Java Technology in an FPGA.- Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers.- The Chess Monster Hydra.- Arithmetic 3.- FPGA-Efficient Hybrid LUT/CORDIC Architecture.- A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays.- Design and Implementation of a CFAR Processor for Target Detection.- Signal Processing 2.- A Parallel FFT Architecture for FPGAs.- FPGA Custom DSP for ECG Signal Analysis and Compression.- FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems.- System-on-Chip 2.- Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design.- A Low Power FPAA for Wide Band Applications.- Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs.- Image Processing 2.- Real-Time Computation of the Generalized Hough Transform.- Minimum Sum of Absolute Differences Implementation in a Single FPGA Device.- Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic.- Cryptography and Compression.- High Throughput Serpent Encryption Implementation.- Implementation of Elliptic Curve Cryptosystems over GF(2 ) in Optimal Normal Basis on a Reconfigurable Computer.- Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V.- Network Applications and Architectures.- A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses.- Multithreading in a Hyper-programmable Platform for Networked Systems.- An Environment for Exploring Data-Driven Architectures.- FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.- Network on Chip and Adaptive Architectures.- A Dynamic NoC Approach for Communication in Reconfigurable Devices.- Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.- FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.- A Structured Methodology for System-on-an-FPGA Design.- Debugging and Test.- Secure Logic Synthesis.- Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.- The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead.- Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory.- Organic and Biology Computing (Poster).- FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head.- FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.- Processing Repetitive Sequence Structures with Mismatches at Streaming Rate.- Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA.- FPGA Implementation of the Ridge Line Following Fingerprint Algorithm.- Security and Cryptography (Poster).- A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.- Flow Monitoring in High-Speed Networks with 2D Hash Tables.- A VHDL Generator for Elliptic Curve Cryptography.- FPGA-Based Parallel Comparison of Run-Length-Encoded Strings.- Real Environments Image Labelling Based on Reconfigurable Architectures.- Mapping and Compilers (Poster).- Object Oriented Programming Paradigms for the VHDL.- Using Reconfigurable Hardware Through Web Services in Distributed Applications.- Data Reuse in Configurable Architectures with RAM Blocks.- A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development.- AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits.- Architectures (Poster).- A Self-Reconfiguration Framework for Multiprocessor CSoPCs.- A Virtual File System for Dynamically Reconfigurable FPGAs.- Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array.- Design and Implementation of the Memory Scheduler for the PC-Based Router.- Algorithms and IP (Poster).- Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach.- Intellectual Property Protection for RNS Circuits on FPGAs.- FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines.- Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector.- Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA.- Image Processing (Poster).- FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot.- Real-Time Detection of Moving Objects.- Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs.- Versatile Imaging Architecture Based on a System on Chip.- A Hardware Implementation of a Content Based Image Retrieval Algorithm.- PhD Forum (Poster).- Optimization Algorithms for Dynamic Reconfigurable Embedded Systems.- Low Power Reconfigurable Devices.- Code Re-ordering for a Class of Reconfigurable Microprocessors.- Design Space Exploration for Distributed Hardware Reconfigurable Systems.- TPR: Three-D Place and Route for FPGAs.- Implementing Graphics Shaders Using FPGAs.- Preemptive Hardware Task Management.- Automated Speculation and Parallelism in High Performance Network Applications.- Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems.- A Specific Scheduling Flow for Dynamically Reconfigurable Hardware.- Design and Evaluation of an FPGA Architecture for Software Protection.- Scalable Defect Tolerance Beyond the SIA Roadmap.- Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems.- Optimized Field Programmable Gate Array Based Function Evaluation.- MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.- A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware.- On Computing Maximum Likelihood Phylogeny Using FPGA.- Minimising Reconfiguration Overheads in Embedded Applications (Abstract).- Application Specific Small-Scale Reconfigurability.- Efficient FPGA-Based Security Kernels.

Produktinformationen

Titel: Field Programmable Logic and Application
Untertitel: 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings
Editor:
EAN: 9783540301172
Format: E-Book (pdf)
Hersteller: Springer Berlin Heidelberg
Genre: IT & Internet
Veröffentlichung: 11.08.2004
Digitaler Kopierschutz: Wasserzeichen
Anzahl Seiten: 1202

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