Computer Organization and Design

The best-selling computer organization book is thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies, with examples highlighting the latest processor designs and benchmarking standards. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.

A companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text.

• Covers the revolutionary change from sequential to parallel computing, with a new chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics.

• Includes a new appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing.

• Describes a novel approach to measuring multicore performance--the Roofline model--with benchmarks and analysis for the AMD Opteron X4, Intel Xeon 5000, Sun UltraSPARC T2, and IBM Cell.

• Includes new content on Flash memory and Virtual Machines.

• Provides a large, stimulating set of new exercises, covering almost 200 pages.

• Features the AMD Opteron X4 and Intel Nehalem as real-world examples throughout the book.

• Updates all processor performance examples using the SPEC CPU2006 suite.

  Computer Organization and Design, Fourth Edition, provides a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors.

This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Along with its increased coverage of parallelism, this new edition offers new content on Flash memory and virtual machines as well as a new and important appendix written by industry experts covering the emergence and importance of the modern GPU (graphics processing unit), the highly parallel, highly multithreaded multiprocessor optimized for visual computing.

This book contains a new exercise paradigm that allows instructors to reconfigure the 600 exercises included in the book to generate new exercises and solutions of their own. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them as well as advanced content for further study and a search utility for finding content on the CD and in the printed text.

This text is designed for professional digital system designers, programmers, application developers, and system software developers as well as undergraduate students in Computer Science, Computer Engineering and Electrical Engineering courses in Computer Organization, Computer Design.

A new exercise paradigm allows instructors to reconfigure the 600 exercises included in the book to easily generate new exercises and solutions of their own.

The companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. For the convenience of readers who have purchased an ebook edition or who may have misplaced the CD-ROM, all CD content is available as a download at http://bit.ly/12XinUx.

Autorentext

ACM named David A. Patterson a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. David A. Patterson is the Pardee Chair of Computer Science, Emeritus at the University of California Berkeley. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.

Inhalt

Computer Abstractions and Technology; Instructions: Language of the Computer; Arithmetic for Computers; Assessing and Understanding Performance; The Processor; Enhancing Performance with Pipelining; Large and Fast: Exploiting Memory Hierarchy; Storage, Networks and Other Peripherals; Multiprocessors and Clusters; Mapping Control to Hardware; A Survey of RISC ARchitectures for Desktop, SErver, and Embedded Computers.